The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to a reference cell with various load circuits compensating for corresponding source side loading effects when reading non-volatile memory.
A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells that are field effect transistors (FETs). Each FET, or flash, memory cell includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block. The flash memory cell provides for non-volatile data storage.
A typical configuration of a flash memory cell consists of a thin, high-quality tunnel oxide layer sandwiched between a conducting polysilicon floating gate and a crystalline silicon semiconductor substrate. The tunnel oxide layer is typically composed of silicon oxide (SixOy). The substrate includes a source region and a drain region that can be separated by an underlying channel region. A control gate is provided adjacent to the floating gate, and is separated by an interpoly dielectric. Typically, the interpoly dielectric can be composed of an oxide-nitride-oxide (ONO) structure.
The flash memory cell stores data by holding charge within the floating gate. In a write operation, charge can be placed on the floating gate through hot electron injection, or Fowler-Nordheim (F-N) tunneling. In addition, F-N tunneling can be typically used for erasing the flash memory cell through the removal of charge on the floating gate.
Prior Art FIG. 1 is a circuit diagram of a portion of an array 100 of memory cells arranged in a NOR type of configuration. The array 100 contains non-volatile flash memory cells arranged in rows and columns. A plurality of word lines 110, or select lines, are coupled to a plurality of rows of memory cells. The plurality of word lines 110 include WL1, WL2, WL3, and WL4. Each of the plurality of word lines 110 are coupled to gate regions of memory cells in their respective rows. For example, WL1 is coupled to gate regions of memory cells defined by WL1-BL1, WL1-BL2, WL1-BL3, and WL1-BL4, etc.
In addition, a plurality of bit lines 120 are coupled to a plurality columns of memory cells. The plurality of bit lines 120 include BL1, BL2, BL3, and BL4. The plurality of bit lines are coupled to drain regions of memory cells in their respective columns. For example, BL1 is coupled to drain regions of memory cells defined by WL1-BL1, WL2-BL1, WL3-BL1, and WL4-BL1.
In the array 100 of memory cells, a particular memory cell can be identified and read to determine if the cell is programmed or erased by applying the correct voltages to a corresponding bit line and word line. For example, in order to read the memory cell 140, appropriate voltages would be applied to bit line BL2 and word line WL2 to read the state of memory cell 140. Correspondingly, in order to read the memory cell 150, appropriate voltages would be applied to bit line BL4 and word line WL2 to read the state of memory cell 150.
A plurality of source lines 130 are coupled to each of the rows of memory cells. The plurality of source lines include SL1, SL2, SL3, and SL4. Each of the plurality of source lines 130 are coupled to source regions of memory cells in their respective rows. For example, SL1 is coupled to source regions of memory cells defined by WL1-BL1, WL1-BL2, WL1-BL3, and WL1-BL4, etc.
The plurality of source lines 130 are used to read current from identified memory cells in the array 100 of memory cells. For example, in order to determine the state of memory cell 140, appropriate voltages are applied to BL2 and WL2. When selected and activated, the memory cell 140 will produce a current through its respective source region that is read from an source line node 132 corresponding to its respective source line, SL2. Correspondingly, source line SL1 is coupled to source line node 131, SL3 is coupled to source line node 133, and SL4 is coupled to source line node 134.
Thereafter, the current from memory cell 140 is compared to a reference current of an approximately identical memory cell to determine its state, whether it is programmed (0) or erased (1). If the current from memory cell 140 is less than the reference current, then the memory cell 140 is in a programmed state (0), and its corresponding threshold voltage (VT) is very high and should be higher than the threshold voltage of the reference cell (VTRef). Correspondingly, if the current from memory cell 140 is more than the reference current, then the memory cell 140 is in an erased state (1), and its corresponding VT should be lower than VTRef.
A problem with source side loading effects exists when reading memory cells in a row of memory cells in the array 100 of memory cells. For flash memory technology, the cells in an array 100 are erased simultaneously. After the erase process, the threshold voltage for each cell is checked individually. Current from each of the individual memory cells in the array 100 is compared to current from the reference cell to determine if the memory cell has been erased.
For NOR type flash configurations, the source lines are formed by implantation on silicon. As a material, silicon has a high unit resistance value. Since the resistance is relatively high, there are some source side loading effects. In particular, the resistance value of a particular source line increases as more and more of the source line is used to access memory cells along a row of memory cells.
Since the array is laid out more or less uniformly, the same distance of source line connects source regions of adjoining memory cells in a row of memory cells. That distance can be associated with a unit source side resistance value (Rs). For example, in the row of memory cells identified by SL2, the source side resistance for each of the memory cells is approximately as follows, in the following format, memory cell;resistance value: WL2-BL1;Rs, WL2-BL2;2Rs, WL2-BL3;3Rs, and WL2-BL4;4Rs.
Moreover, the source side loading effect will cause variation in the threshold voltages in a row of memory cells based on the location of the memory cell being accessed. For example, assuming that all the bits or memory cells in the array 100 of memory cells have the same approximate true VT, when the same voltage is applied to respective word lines and bit lines, the same current and threshold voltage should approximately be read no matter the location of the memory device in the array 100, and in particular, along a single row of memory cells in the array 100.
However, because of the source side loading effects, the threshold voltage will increase the further away from the source line node of the respective source line from which the current is read. For example, for bit (WL2-BL4), the source side resistance is equal to 4Rs, and the corresponding voltage increase for its threshold voltage would be equal to 4Rs times the current. For bit (WL2-BL2), the source side resistance is less and is equal to 2Rs, and the corresponding voltage increase for its threshold voltage would be equal to 2Rs times the current.
Since the voltage drop at the source side for bits (WL2-BL4 and WL2-BL2) are different, even though the true VT is approximately identical for the bits (WL2-BL4 and WL2-BL2), during a read operation, the bit (WL2-BL2) will read more current because of lower source side resistance (2Rs), than for bit (WL2-BL4) with source side resistance (4Rs). As such, it appears that bit (WL2-BL2) has a lower VT than the VT for bit (WL2-BL4), when in fact the two VTs are approximately equal. In addition, the apparent distribution of threshold voltages will increase due to the faulty readings of VT due to the source side loading effects.
The source side loading effects leads to over-erasure of memory cells within the array 100. In particular, during an erase operation, even though all the bits in the array 100 were erased to the same VT, the bits with higher source side resistance (e.g., WL2-BL4) would appear to still be programmed, since its current is reduced. As such, the array 100 would be subjected to a further erase pulse, thereby lowering VT for the memory cells throughout the array 100. This causes memory cells to become over-erased (e.g., VT less than 0), or for memory cells with lower source side resistance (e.g., WL2-BL2) to appear to be over-erased. Over-erasure of bits within the array 100 can cause bitline to bitline leakage within the array 100, leading to faulty readings from memory cells in a column having an over-erased memory cell.
In addition, to compensate for the increased distribution of threshold voltages due to the source side loading effects, the threshold voltages defining the program state and the erase state must be separated by a larger margin of voltage. This inhibits performance of 2 bit or 4 bit memory cell architecture, since the tolerance is small.
The present invention provides a reference cell with various load circuits compensating for source side loading effects in a non-volatile memory. As such, embodiments of the present invention provide for truer voltage threshold readings of memory cells in an array of memory cells. Embodiments of the present invention also provide for load circuits capable of compacting the voltage threshold distribution in an array of memory cells. Also, embodiments of the present invention provide for load circuits capable of wider margins between voltage thresholds of a program and erase state, thereby allowing for more efficient 2-bit or 4-bit multi-level cell architectures.
Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of resistance or load circuits. The reference cell provides a reference current for the non-volatile memory comprising a plurality of memory cells. The reference cell is approximately identical to at least one of the plurality of memory cells.
At least one of the plurality of load circuits comprises a select transistor coupled to a plurality of resistors. The plurality of resistors are coupled in series. Each of the plurality of load circuits matches a source side loading effect of a corresponding memory cell in a non-volatile memory. As such, each of the plurality of load circuits reduces the reference current equal to a reduction in current from a corresponding memory cell due to its respective source side loading effect.
In particular, one of the plurality of load circuits, an mth load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The mth load circuit matches a source side loading effect of a corresponding mth memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.